Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1990. This study investigates the memory and bandwidth needs at a single switching node in an Asynchronous Transfer Mode (ATM) communications network. Matrix analysis and computer simulation methods were used, and their results compared and contrasted. Three types of switching architectures (input buffering, output buffering, and shared output buffering) were analyzed in the computer simulation method, and the output buffering architecture was analyzed with matrix methods. The two network resources considered were packet loss probability and packet transmission delay. The traffic sources were modeled with a Markov process describing correlated bursty packet arrivals. The model produced bursts of packets alternating with silences, and allows specification of two moments each for the burst and silence length distribution; it also allows variation in the correlation between packets within a burst. The parameters of the traffic model were varied in different combinations, and their relative impacts on resource needs were evaluated. Results showed that the shared output buffering architecture allows far better performance than the other two architectures. However, vital dependencies emerge between the burst length of traffic sources and the performance of all three switch architectures. The two methods produced almost identical results on a common example, validating the accuracy of the computer simulation method.

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